Non-volatile semiconductor memory devices have been used extensively throughout the electronics industry for many years now. These cells typically employ floating gate devices in which a floating gate member is completely surrounded by an insulative layer such as silicon dioxide. Usually, a polycrystalline silicon (i.e., polysilicon) layer is used to form the floating gate members. Charge is transferred to the floating gate through a variety of mechanisms which include avalanche injection, channel injection, tunnelling, etc.
According to the operating principles of these devices, the charge on the floating gate affects the surface channel conductivity within the cell. If the conductivity is above a certain level, the cell is deemed to be programmed in one binary state, and if the conductivity is below another level, it is deemed to be programmed in the opposite binary state. Memory devices comprising arrays of such cells are referred to in the prior art as EPROMs or EEPROMs.
A type of non-volatile memory device, known as a flash EPROM or flash EEPROM, is one in which the entire array of cells can be erased simultaneously. That is, individual cells or groups of cells are not separately erasable as in ordinary EPROMs or EEPROMs. A flash EEPROM device is disclosed in co-pending application Ser. No. 07/253,775, filed Oct. 15, 1988, entitled "Low Voltage EEPROM Cell", which is assigned to the assignee of the present invention. U.S. Pat. Nos. 4,698,787 and 4,868,619 also disclose EEPROM devices fabricated to have an asymmetrical source/drain profile. Each of these prior art references discloses an electrically erasable programmable memory device which is programmed by hot-electron injection from the channel onto the floating gate and is erased by Fowler-Nordheim Tunnelling from the floating gate to the substrate.
In the past, EPROM and EEPROM cells have commonly been fabricated by initially defining active regions surrounded by field isolation regions. The field isolation is provided by means of relatively thick field oxide regions. Individual memory cells are then formed within these active regions. In the construction of a large memory array, it is conventional to form elongated, parallel source/drain regions which are sometimes referred to as bit lines. These elongated bit lines extend across the length of the array to provide electrical connection to columns of cells formed therebetween.
Running generally perpendicular to these bit lines are a plurality of polysilicon strips, frequently referred to as wordlines. Each of these polysilicon wordlines are coupled to the control gates within a single row of cells in the array. Together, the bit lines and wordlines provide a means for reading and writing information to individual memory cells.
One of the problems that arises in prior art processes is that, in order to form a continuous source or drain bit line within the substrate, selected portions of field oxide must be removed from the surface of the substrate. Once removed, ordinary ion implantation steps are typically employed to properly dope the substrate and the regions where the bit lines are to be located. A very high etching selectivity is required between the field oxide and the underlying silicon substrate during the etching step which removes the field oxide. Overetching into the substrate damages the substrate surfaces in that region. A consequence of this type of surface damage is an erase distribution problem within the array. That is, certain cells erase at a much faster rate than other cells within the array. Of course, such variation in erase performance is undesirable.
It is also beneficial to reduce the overall dimension of the memory cell in order to increase the density of the memory array. Traditionally, one of the chief impediments to reducing cell size has been the contact-to-gate spacing requirements. In the past, a spacing of greater than 0.5 microns between the polysilicon control gate and the drain contacts has been required to guard against accidental shorts. This spacing requirement generally limited the overall achievable cell density. The minimum contact-to-gate spacing has also been limited in prior processes by the step coverage restrictions over the gate members.
As will be seen, the present invention discloses a process for fabricating flash EPROM devices which obviates the need to remove selected field oxide regions when forming elongated, buried bit lines within the array. The invented process is characterized by its highly self-aligned contact structure and by its novel use of titanium silicide and titanium nitride, among other materials, to form electrical conductors over field oxide regions.
Other prior art known to applicant include an article entitled, "Titanium Disilicide Self-Aligned Source/Drain+Gate Technology", by Lau et al., IEDM, 1982, which generally describes the use of titanium disilicide. Formation of titanium nitride films in a semiconductor process is also described generally in "LPCVD Titanium Nitride-Deposition, Properties, and Application to ULSI" by Pintchovski et al., Materials Research Society, 1989; "Microstructure and Electrical Properties of Titanium Nitride Diffusion Barrier Films Sputter from a Composite Target" by Wei et al., Materials Research Society, 1989; and "Titanium Nitride Deposition in a Cold Wall CVD Reactor" by A. Sherman, Materials Research Society, 1989. A trench-self-aligned isolation process technology for an EPROM memory cell structure is also described in an article entitled, "A 3.6 .mu.m.sup.2 Memory Cell Structure For 16MB EPROMS", by Hisamune et al., IEDM 1989, p. 583-586.